1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and the semiconductor device, and particularly relates to a manufacturing method of a semiconductor device in which semiconductor elements having favorable characteristics are formed and the semiconductor device.
2. Description of the Related Art
In recent semiconductor devices, in order to achieve a reduction in the resistance of polysilicon wiring and a diffusion layer, a salicide metal layer is formed on the surface sides thereof. In forming the salicide metal layer, the formation of the uniform salicide metal layer on the polysilicon wiring and a wiring layer is demanded. A manufacturing process to form such a salicide metal layer is disclosed, for example, in Japanese Patent Laid-open No. 8-250716.
The manufacturing process of a related semiconductor device, which is disclosed in Japanese Patent Laid-open No. 8-250716 and so on, will be explained based on FIG. 1 to FIG. 3. FIG. 1 is a diagram showing a section of the related semiconductor device before the salicide metal layer is formed, and FIG. 2 is a diagram showing a section of the related semiconductor device after the salicide metal layer is formed. FIG. 3 is a plan view of FIG. 2.
As shown in FIG. 1, to form the uniform the salicide metal layer, cleaning with dilute HF is performed before the salicide metal layer is formed. Namely, oxide films and particles, which are naturally formed on the surfaces of P+ diffusion regions 10 and 10, the surfaces of N+ diffusion regions 12 and 12, and the surfaces of the gate electrodes 14 made of a polysilicon layer, are removed.
Thereafter, as shown in FIG. 2, the salicide metal layer is formed on the surfaces of the P+ diffusion regions 10 and 10, the surfaces of the N+ diffusion regions 12 and 12, and the surfaces of the gate electrodes 14 made of the polysilicon layer.
However, in the related manufacturing method, there is a problem that during cleaning treatment with dilute HF, a silicon oxide film (SiO2) which forms a buried insulating film 20 for element isolation dissolves due to the dilute HF. In other words, there is a problem that SiO2 and HF react with each other as shown in the following formula to thereby precipitate water mark.SiO2+4HF→SiF4+2H2O
Particularly as shown in FIG. 3, when this precipitated water mark 30 adheres to the surfaces of P+ diffusion regions 10 and 10, the surfaces of N+ diffusion regions 12 and 12, and the surfaces of the gate electrodes 14 made of the polysilicon layer, the water mark 30 functions like a mask material. Hence, as shown in FIG. 2, the salicide metal layer is not formed in portions corresponding to the water mark 30, and as a result, the uniform saliside metal layer cannot be obtained. If the uniform salicide metal layer is not formed, the resistance of the P+ diffusion regions 10 and 10, the N+ diffusion regions 12 and 12, and the gate electrodes 14 made of the polysilicon layer increases, which deteriorates characteristics of MISFETs as semiconductor elements.
Moreover, in the semiconductor device shown in FIG. 2, the height of the buried insulating film 20 and the height of the gate electrode 14 are different, thereby a step occurs between the buried insulating film 20 and the gate electrode 14. Therefore, there is a problem that when an interlayer dielectric is formed thereon, the planarity of the interlayer dielectric is deteriorated.